1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device, which improves 2-bit pre-fetch access time in a burst mode of a synchronized Dynamic Random Access Memory (SDRAM).
2. Description of the Related Art
A synchronized DRAM (hereafter referred to simply as SDRAM) is a DRAM that performs internal operations in synchronous with a system-supplied clock, and is capable of faster operation than an ordinary DRAM. This SDRAM is also supplied with system-supplied command signals, which specify operating modes. By internally decoding these supplied command signals, the SDRAM determines the system-requested operating mode, and, for example, outputs read data in accordance with a specified operating mode.
One of the aforementioned operating modes is a burst mode. Relative to an externally-supplied address, this burst mode treats that address as the point of origin and outputs memory data of consecutive addresses. It also specifies the number of consecutive output bits as 2 bits, 4 bits or 8 bits.
With such a burst mode, an SDRAM internally generates consecutive addresses based on the external address, decodes those addresses and outputs their memory data. However, it is inefficient that one internal address is generated in the 2-bit burst mode, three internal addresses are generated in the 4-bit burst mode, and seven internal addresses are generated in the 8-bit burst mode.
Accordingly, SDRAM divides the internal memory cell array into an odd address memory cell array and an even address memory cell array, and in the burst mode, for externally-supplied or internally-generated addresses, supplies addresses minus their least significant bits to column decoders in the odd address memory cell array and even address memory cell array. Such an architecture makes it possible to output 2-bit memory data sequentially at all times. This architecture is called a 2-bit pre-fetch circuit.
FIG. 13 depicts an example of a conventional SDRAM 2-bit pre-fetch circuit. In this example, the memory cell array is divided into an odd address memory cell array 10 and even address memory cell array 20. Then, address predecoders 11, 21 and address main decoders 12, 22 are provided for each of the memory cell arrays 10, 20. Furthermore, the output from each memory cell array 10, 20 is amplified by a data bus amplifier 13, 23.
SDRAM operates in synchronous with a clock CLK supplied by the system. Therefore, based on the timing of the clock 31 output from the clock buffer 30 incorporating this clock CLK, a command signal 2 (Comm) is latched by a command latch & decoder 32, and an address signal 3 (Add) (in this example, 10 bits from a0-a9) is latched by an address buffer 33. Then, an address signal a3-a9 from the address buffer 33 is latched by an address latch 38 based on the timing of an address latch clock 35 generated by the comma nd latch & decoder 32. Also, based on the same clock 35, an address signal a1-a2 is latched by an address latch & counter 39.
An address signal a3-a9 is supplied as-is to odd and even address predecoders 11, 21. Meanwhile , address a1, a2 is supplied as-is to the odd address predecoder 11. Also, address a1, a2 is supplied to the even address predecoder in accordance with the value of the least significant ad dress a0, that is, according to whether it is odd or even, either as-is as a latched address 44 or as a new shifted address 48 which the address arithmetic circuit 46 increments by 1 the address a1, a2.
Thus, when the external address is even, the even memory data 24 amplified by the even data bus amplifier 23 is latched by an output data latch circuit 16 based on clock 56 timing, and then the odd memory data 14 amplified by the odd data bus amplifier 13 is latched by an output data latch circuit 26 based on clock 57 timing, and even and odd data are sequentially output in that order.
Further, when the external address is odd, odd memory data 14 is latched by an output data latch circuit 16, and even memory data is latched by an output data latch circuit 26, based on timing supplied by clocks 56, 57, respectively, and odd and even data are sequentially output in that order.
FIG. 14 is a timing chart depicting the operation of the circuitry depicted in the above-described FIG. 13. With SDRAM, a command signal 2 which instructs read is supplied in synchronous with the rise edge of the external clock CLK, and an external address 3 is supplied based on the same timing. Then, address 42 (a9-a3) and address 44 (a1, a2), which were latched by address latch circuits 38, 39, are output based on time t1 timing.
However, in the case of an externally-supplied odd address, a shifted address 48, which is generated by adding 1 to an address a1, a2, must be supplied to the even address predecoder 21. In the figure, this shifted address 48 is generated at time t2. As a result, even if an odd address 58 (a9-a1) is generated on the basis of time t2 timing, an even address 60 (a9-a1) is not generated until time t3. Therefore, once both addresses 58 and 60 have been generated, and following the read time tread of the cell data in the memory cell arrays 10, 20, a data bus amplifier latch signal 55 is generated by a clock generator 54 based on time t4 timing, and both data are latched by the data bus amplifiers 13, 23. Then, read data is latched by an output data latch circuit 16 on the basis of clock 56 timing, following which, read data is latched by an output data latch circuit 26 on the basis of clock 57 timing.
Therefore, CAS delay time t.sub.cac, from the clock CLK rise timing, by which a read command 2 is supplied, until time t6, when the initial read data is output in th5 terminal Dout, is fairly long.
In addition, in a 4-bit burst mode, the above-described 2-bit pre-fetch operation is performed two times, and in an 8-bit burst mode, the above-described 2-bit pre-fetch operation is performed four times. Thus, the above-described CAS delay timetfFt.sub.cac, is required for each 2-bit pre-fetch operation.
This kind of delay time is not suitable for burst mode read time aimed at highspeed operation, and the reduction of CAS delay time t.sub.CAC is desirable.
Therefore, it is an object of the present invention to provide a semiconductor memory device that speeds up the 2-bit pre-fetch operation in the burst mode.
In addition, another object of the present invention is to provide a semiconductor memory device that reduces the CAS delay time at least until the initial output data in a burst mode 2-bit pre-fetch operation is output.